R&S Measurement Campaign

GaN MPPT Phase: R&S / ZES Measurement Campaign

Procedures for the measurement campaign on the EOI-A65-6A GaN MPPT phase boards using the sponsored Rohde & Schwarz and ZES ZIMMER equipment. Each experiment is written to be run start-to-finish by one engineer and to produce both an engineering result and a publishable figure.

Purpose

Three goals, in priority order:

1. Resolve open engineering questions. Idle dissipation, dead-time optimum, and output current-sense accuracy are all unresolved and all measurable with this equipment.
2. Calibrate and characterise the product. The default configuration ships with calibrated = false and placeholder sensor gains.
3. Produce publishable content. Each experiment below defines its hero shot and which instrument capability makes it possible.

An experiment only belongs in this campaign if the instrument is load-bearing, i.e. the result is not obtainable with ordinary bench gear. Otherwise it is just a measurement, not a story.

Equipment

Instrument	Role	Capability that matters here
ZES ZIMMER LMG671	Power / efficiency reference	0.015%-class accuracy; up to 7 simultaneously-sampled channels; microwatt-resolution DC; transient recorder
R&S MXO34	Waveform + spectrum	12-bit always-on; ~4.5 M acquisitions/s; ~45 k FFT/s live spectrum; zone trigger; deep memory
R&S RT-ZISO	Isolated probe	Galvanic isolation with CMRR that survives nanosecond edges. There is no gate node on this board, so its job here is the bootstrap rail, high-side VDS and the current-shunt terminals; see Floating nodes

Before promising numbers publicly, confirm the exact bandwidth and isolation rating of the RT-ZISO model supplied, and confirm that the LMG671 includes the transient-recording and data-logger options. Experiments 4, 5 and the tracking-efficiency work depend on those options.

Device under test

Values below are taken from Open-SEC Firmware/src/hardware/eoia656a.h and eoia656a.c. Re-check them against the branch under test before quoting them.

Parameter	Value	Source
Hardware name	EOI-A65-6A	HW_NAME
Topology	Synchronous boost, GaN half bridge (EPC23102)	HW_TOPOLOGY_BOOST
Gate drive	Integrated in the EPC23102 ePower stage. Neither gate is brought out of the package. The only accessible signals are two ground-referenced 3.3 V logic inputs	P2_PWM_LS (PA10), P2_EN_HS (PA11), HW_NO_AND_GATE
Switching frequency	100 kHz	HW_SWITCHINGFREQUENCY
Control loop rate	20 kHz (Ts = 50 us)	HW_CONTROLLERFREQUENCY
Dead time (rising / falling)	8 ns / 8 ns	HW_DEADTIMERISING, HW_DEADTIMEFALLING
Inductor	HW_L = 38 uH, the value at the 8 A operating point, not the 47 uH nominal of L1 (7443634700). DCR 12 mOhm	HW_L, HW_RLINT
Declared Clow / Chigh	100 uF / 70 uF. Chigh is the per-phase share of the ~560 uF baseboard bus (3 x 180 uF plus ceramics) divided across 8 slots, not the physical bulk	HW_CLOW, HW_CHIGH
Overvoltage fault (both rails)	63 V	HW_LIMIT_HS_VOLTAGE_HARD
Overcurrent fault (both rails)	13 A	HW_LIMIT_HS_CURRENT_HARD
Soft current limit	9 A	HighSideCurrentLimitSoft
Current sensors	2 x INA253A2, 2 mOhm integrated shunt, 200 mV/A, zero at 0.5 V	Isense.SchDoc
Phase count per baseboard	8, interleaved via PHASE_EN; startup staggered 200 ms per CAN ID	mppt.c
Temperature sensors	NT1 = ambient, NT2 = FET/heatsink, 100 k NTC, B = 4330	Temperature_B

The GaN devices are rated 100 V. The project README recommends 75 V nominal maximum for system use. Do not exceed that during these experiments regardless of what the firmware fault thresholds allow.

Safety and bench hygiene

Grounding

Verify the grounding topology on your specific board before connecting any ground-referenced instrument.

On the EOI-A65-6A the INA253 sense elements sit in the positive rail (PANEL_IN+ -> Isense+ / Isense- -> Vin, and likewise on the output), so input and output grounds are common. Single-ended, ground-referenced probing of the switch node is therefore permissible.

This differs from the older SEC-B80-8A described in the repository README, which uses ground-path current sensing. On that hardware, shorting input and output grounds together, which any two ground-referenced scope probes will do, can destroy the board. If there is any doubt which hardware is on the bench, use the RT-ZISO and treat every node as floating.

Probing rules

• There is no gate node on this board. The EPC23102 integrates both gate drivers, so neither V_GS is accessible with any probe. What leaves the MCU is two ground-referenced 3.3 V logic lines, P2_PWM_LS (PA10) and P2_EN_HS (PA11), driven by HRTIM TB1/TB2 with hardware dead-time insertion. Since the AND gate was removed (HW_NO_AND_GATE) these reach the driver directly, so they show the commanded dead time as the driver receives it. A 10:1 passive probe is sufficient; the isolated probe is wasted here.
• Never reference a ground-referenced probe to a node that floats to SW. That rules out the bootstrap rail, high-side V_DS and the shunt terminals. Use the RT-ZISO for those, see Floating nodes.
• At ~55 V with nanosecond edges, probe ground lead length dominates the measurement. Use a ground spring, not a lead, for switch-node captures.
• The LMG671 inputs are individually isolated; multi-channel connection across the converter is safe.
• De-skew all channels before any v*i product or timing measurement. Record the de-skew values in the log.

Electrical

• Treat the DC bus as hazardous above 50 V. Discharge the output bulk capacitance before rework; the baseboard carries substantial bulk on the battery side.
• Set the source current limit at or below 9 A per phase before enabling the output.
• Keep a thermal camera or the on-board NTC telemetry visible during any run that changes dead time or disables protections.

Common bench setup

Connections

Node	Instrument	Notes
Panel input (V, I)	LMG671 ch1	Kelvin sense at the board connector, not at the supply
Battery output (V, I)	LMG671 ch2	Same reference plane convention as the input
Individual phase outputs	LMG671 ch3 to ch7	Up to 5 phases alongside both terminals; see channel budget note
Switch node (SW)	MXO34 ch1	Ground spring, shortest possible loop. This channel carries the dead-time information, see Experiment 3
Driver logic input P2_PWM_LS (PA10)	MXO34 ch2	Ground-referenced 3.3 V logic, 10:1 passive probe. A driver input, not a gate
Floating node under test	RT-ZISO on MXO34 ch3	Bootstrap rail, high-side VDS, shunt terminals or inductor voltage; pick per experiment from Floating nodes. When the isolated probe is not in use, put P2_EN_HS (PA11) here to capture both logic edges and read the commanded dead time directly
CURR_SE (INA253 output, before R12)	MXO34 ch4	Pre-filter node; this is where clipping is visible

Channel budget: the LMG671 provides at most 7 channels. With both terminals instrumented, 5 phases can be measured simultaneously. To capture all 8 phase currents at once, drop the terminal channels and derive totals by summation.

Floating nodes and what the isolated probe is for

Because no gate is accessible, the RT-ZISO's job on this board is a different set of measurements. Ranked by how much the result depends on the probe being isolated rather than merely differential:

#	Node	What it yields	Caveat
1	Bootstrap rail, BOOT - SW	The closest available proxy for high-side drive health: CBOOT droop per cycle, refresh behaviour, and margin to the high-side UVLO at the D ~ 0.7 end of the boost range	Only if the bootstrap capacitor is external and probeable on this layout. Confirm on the schematic before planning around it, some ePower stages integrate it. See #Open items
2	High-side VDS, VIN - SW	The high-side device's Eon and Eoff. Ground-referenced probing can only ever reach the low-side device	De-skew against the current channel before any v*i integration, and state the de-skew value with the result
3	Shunt terminals, Isense+ - Isense-	Separates "the shunt current genuinely has flat tops" from "the INA253 output stage is clipping or slew-limited". That is the question Experiment 2 currently answers from one side only	2 mOhm at 13 A is 26 mV differential riding on a 55 V slewing common mode. Needs the RT-ZISO's CMRR; an ordinary 1000:1 HV differential probe will not resolve it. Kelvin access to both terminals must be confirmed
4	Inductor voltage, SW - output node	VL/L integrates to inductor current with no current probe and no shunt bandwidth limit, and it measures L at the operating point	See the note below
5	Package PGND - analogue GND	Power-loop ground bounce at nanosecond edges. Turns the ground-spring rule into a number and probably accounts for part of the current-sense noise floor	Small differential signal against a large common mode; average over many acquisitions

On item 4: HW_L is set to 38 uH against a 47 uH nominal part, deliberately, because the current-limit law's effective per-step gain scales with HW_L/L_actual. That derating has never been checked on the bench. Measuring inductor voltage gives L at the 8 A operating point directly and either confirms the constant or corrects it, which makes this the cheapest firmware-relevant result in the campaign.

If gate-level waveforms are wanted for publication, the only route is a discrete GaN plus external driver test vehicle, or an EPC evaluation board carrying the same die. It cannot be done on EOI-A65-6A, and no probe changes that.

Firmware preparation

1. Build the HW_EOIA65_6A target in the Debug configuration. Do not use the Simulation build, which substitutes a model for the power stage.
2. Flash via ST-Link and TAG-Connect (J2, TC2030-NL).
3. Connect USB for the serial terminal. Available commands: help, ping, status, sens, hwinfo, config, config_read, config_write, config_default, reboot.
4. Record the firmware version and git commit hash in the log before every session.

Telemetry available without instruments

• Serial terminal: sens and status.
• calibrate_mppt.py PORT --read-val polls Iind, Ihigh, Ilow, Vlow, Vhigh, TempHeatsink, TempAmbient at 2 Hz.
• CAN: status frame every 1000 ms, power frame every 500 ms. See MPPT_ID32+0-4.dbc.
• Firmware scope buffer: scope_start(), up to CONVERTER_SCOPE_CHANNELS channels sampled at the 20 kHz control rate.

The firmware scope is the natural cross-validation target for the LMG671, see Experiment 2.

Experiment 1: Idle power teardown

Question: a phase board reaches ~55 C with no power being harvested. Where does every milliwatt go?

Hero instrument: LMG671. Microwatt-resolution DC power is what makes the decomposition credible.

Hero shot: waterfall chart attributing the total idle dissipation to each contributor, with the measured board temperature alongside each step.

Procedure

1. Bring both rails to the nominal operating point (e.g. 35 V in, 55 V out) with the board held in reset. Record LMG671 readings on the 3v3 rail, the 5v2 rail and both HV rails. This is the absolute floor, resistive dividers and leakage only.
2. Release reset with outputEnalbeOnStartup = false. Delta from step 1 = MCU plus analogue front end.
3. Set the MPPT to disabled (MpptState_Disable) so DREN is de-asserted and the bridge is not switching. Confirm via status. Delta from step 2 should be near zero; a large delta means something is switching that should not be.
4. Enable the output with no input power available. Delta from step 3 = power-stage idle loss plus any reverse power flow.
5. At each step, log TempHeatsink (NT2) and TempAmbient (NT1) after a 20-minute thermal soak, plus a thermal camera frame.
6. Check Iind at step 4. The default configuration sets LowSideCurrentMinLimitSoft = -300 mA and PhaseHighSideEnableCurrent = -500 mA, which permit reverse inductor current. If Iind sits at -0.3 A, the phase is actively pumping power from the battery back into the panel. Record the value and compute the drain across all 8 phases.
7. Repeat step 4 with LowSideCurrentMinLimitSoft = 0 to quantify the reverse-flow contribution in isolation.

Expected

Roughly 0.5 to 1.2 W per phase total, with the power stage accounting for the large majority and the MCU 0.10 to 0.15 W. Reverse-current pumping, if present, is the single largest term and shows up as a battery drain far larger than the on-board dissipation.

Pass criteria

Every measured step accounted for within 10% of the sum of its identified contributors. Unattributed residual is itself a finding, so log it rather than hiding it.

Experiment 2: Current-sense verification and calibration

Question: the output current reading is known to run high. Why, and by how much?

Hero instruments: MXO34 (12-bit, to see the pre-filter waveform), RT-ZISO (to see the shunt itself) and LMG671 (as the reference for calibration).

Hero shot: two panels. The CURR_SE waveform overlaid on the true shunt voltage measured differentially across Isense+ / Isense-, both against the smooth inductor current; and a scatter plot of firmware-reported versus LMG671-measured output current, before and after calibration.

Background

The local output capacitance is C18 to C23 (6 x 1 uF 0603) plus C24. The schematic notes "each about 130nF left at 55v", so effective local capacitance at 55 V is roughly 4.8 uF (|Z| approximately 0.33 Ohm at 100 kHz). The ~560 uF of bulk (3 x 180 uF, C9/C10/C65) sits on the baseboard, on the far side of the output shunt, reachable only through ~2 mOhm plus interconnect inductance (|Z| approximately 0.13 Ohm at 200 nH). The lower-impedance path is therefore through the shunt, so roughly 70% of the bridge's pulsed current flows through the sense element rather than being absorbed locally.

The ADC samples this with a 267 ns aperture at a fixed phase locked to the PWM, so the residual ripple contributes a systematic offset rather than averageable noise.

Procedure

1. Capture CURR_SE (MXO34 ch4) together with the low-side gate drive. Confirm the pulse train: approximately zero during D, approximately Iind during (1-D).
2. Look for flat tops. At Iind peaks near 13 A the INA253 output demands 0.5 + 2.6 = 3.1 V, into the supply rail. If the peaks are clipped or slew-limited, the error is nonlinear and no amount of downstream averaging will fix it. This determines whether the software mitigation is worth implementing at all.
3. Cross-check against the shunt itself. Put the RT-ZISO across Isense+ / Isense- and capture the true shunt voltage alongside CURR_SE. If the shunt waveform has clean peaks and CURR_SE is flat-topped, the INA253 is the limiting element and the fix belongs in the amplifier or the sampling instant. If both are flat, the current genuinely is that shape and the fix belongs in the model. One capture settles which, and neither channel alone can.
4. Simultaneously log firmware Ihigh (via --read-val) and LMG671 output current across the full current range at several bus voltages. Plot the error.
5. Repeat for Iind, Vlow and Vhigh. The input shunt carries continuous inductor current and should show a much smaller error; that contrast is the point.
6. Run the calibration procedure using the LMG671 as reference: python calibrate_mppt.py PORT, then menu options 3 to 10 (zero offset and gain for each of input voltage, output voltage, input current, output current), option 11 for the NTC, and option 12 to store to EEPROM.
7. Re-run step 3 and overlay before and after.

Note

Calibration corrects gain and offset. It cannot correct the ripple-induced error, because that error varies with duty cycle and load. Expect a residual that scales with output ripple, and report it as such.

Also worth logging: phase.Ihigh is unfiltered (CURRENT_IN_FORGETING_FACTOR = 0) and feeds the 13 A hard fault directly, so a single sample landing on a ripple peak can cause a nuisance trip. Record any spurious Converter_OutputOverCurrent events observed during the campaign.

Experiment 3: Dead-time optimisation

Question: is 8 ns of dead time causing shoot-through, and what is the optimum?

Hero instrument: MXO34. There is no gate node to probe, so the measurement moves to the switch node, and the capability that matters is the 12-bit ADC: the feature of interest is a 2 to 4 V step sitting on top of the 55 V output rail, resolved with nanosecond timing. An 8-bit scope cannot do this at full vertical range.

Hero shot: three stacked panels sharing an x-axis. The switch-node reverse-conduction pedestal at 8 ns versus the optimum, LMG671 efficiency versus dead time, and Tfets versus dead time. One image, three independent measurements, one causal chain.

Why the switch node, and not the gates

GaN has no body diode. With the gate off it conducts in the third quadrant at a V_SD of roughly 2 to 4 V, dependent on gate bias and current, far worse than a silicon body diode.

Mind the polarity: this is a boost, not a buck. Inductor current flows into the switch node, so during either dead-time interval it must leave through the high-side device, source to drain, which is reverse conduction. SW therefore overshoots to V_high + V_SD for exactly the dead-time window — a pedestal sitting on top of the output rail, not a dip below PGND as it would be in a buck. Both transitions show it.

If inductor current is negative, which the default configuration permits and Experiment 1 step 6 goes looking for, the polarity inverts: the low-side device takes the reverse conduction and the pedestal appears below PGND instead. That makes the pedestal a free indicator of which way the phase is actually pumping.

The pedestal gives three things a gate waveform would not:

• Pedestal width = actual effective dead time, including driver propagation delay and any mismatch between the two channels. This is a bench-side confirmation of the DTxR value rather than a debugger register read, and it is the only way to see the delay the driver itself adds.
• Pedestal area x I_L x f_sw = reverse-conduction loss in watts, computed straight off the waveform and plottable on the same axes as the LMG671 efficiency curve. The loss mechanism and the efficiency penalty are then measured independently and shown to agree, which is a stronger claim than either alone.
• Shoot-through signature: the pedestal disappears, the SW transition goes soft, and input current steps up at fixed load and fixed output voltage.

Prerequisite

The dead-time register write in pwm.c previously OR-ed the computed value onto the HAL default, so most settings landed on the wrong value. This must be fixed before the sweep is meaningful. With the fix in place the commanded value is written directly.

Historical behaviour, for reference. Note that 15 ns and 20 ns were previously identical on hardware, so any earlier sweep would have shown no difference between them:

Commanded	Register count	Actual, before fix	Actual, after fix
8 ns	10	8.33 ns	8.33 ns
10 ns	12	11.67 ns	10.00 ns
15 ns	18	21.67 ns	15.00 ns
20 ns	24	21.67 ns	20.00 ns
30 ns	36	38.33 ns	30.00 ns
40 ns	48	48.33 ns	40.00 ns

Dead-time resolution is 1/(f_HRTIM x 8) = 0.83 ns per count at 150 MHz. If the system clock is changed, the quantisation changes with it.

Procedure

1. Verify the fix in the register: set HW_DEADTIMERISING and HW_DEADTIMEFALLING to 20 ns, halt, and read HRTIM1->sTimerxRegs[1].DTxR. Expect DTR and DTF fields = 24, not 26.
2. Verify it again on the bench: capture SW with a ground spring and measure the pedestal width, with P2_PWM_LS on ch2 for reference. The two should agree once driver propagation delay is subtracted. Record that delay, it is a fixed offset that applies to every point in the sweep.
3. Establish a fixed operating point (for example 35 V in, 55 V out, 4 A per phase) and let it thermally soak for 20 minutes.
4. For each dead-time value in 5, 8, 10, 15, 20, 25, 30, 40 ns: rebuild, flash, soak 20 min, then record LMG671 efficiency, Tfets, Tambient, and an MXO34 capture of SW plus the driver logic input plus inductor current.
5. From each SW capture extract pedestal width and pedestal depth, and compute reverse-conduction loss as pedestal area x inductor current x switching frequency.
6. Plot efficiency, computed reverse-conduction loss and temperature against dead time on a shared axis. The computed loss should track the efficiency roll-off at the long-dead-time end. If it does not, something else dominates, and that is itself the finding.
7. At the short-dead-time end, watch for the pedestal vanishing and for a step in input current at fixed load and fixed output. That is shoot-through, visible without ever seeing a gate.

Expected

A U-shaped efficiency curve. Too little dead time causes shoot-through; too much forces the inductor current through the high-side device in reverse-conduction mode at a significantly higher voltage drop. GaN devices have no body diode, so the reverse-conduction penalty at excessive dead time is steeper than for a silicon bridge, and it is directly visible as a pedestal on SW that both deepens and widens as dead time increases.

Safety

Below 8 ns, shoot-through risk is real. Start at reduced bus voltage and reduced current, watch Tfets continuously, and abort on any rapid temperature rise.

Experiment 4: Interleaving ripple cancellation

Question: does the 8-phase interleaving actually cancel bus ripple as designed?

Hero instrument: MXO34. Roughly 45 k FFT/s makes this live rather than a slideshow of captures.

Hero shot: video of the live input-ripple spectrum while the interleaving is dialled from all-in-phase to fully staggered. The 100 kHz fundamental and its harmonics collapse in real time and 800 kHz emerges. This is the most visually striking result available from this hardware.

Procedure

1. Load all 8 phases at a common operating point.
2. Configure the MXO34 for live FFT of the battery-bus ripple current, span covering 50 kHz to 2 MHz.
3. Baseline: force all phases in phase (identical PHASE_EN alignment). Capture the spectrum.
4. Step the interleaving toward the designed 8-way stagger. Record continuously.
5. Capture the final staggered spectrum and measure the attenuation of the 100 kHz component and the amplitude of the new 800 kHz component.
6. Companion capture: LMG671 transient recorder at 10 MS/s on as many phase currents as channels allow, giving 8 staggered triangle waves in one frame. Note the channel budget constraint.

Expected

Substantial attenuation of the 100 kHz fundamental with energy reappearing at 8 x 100 kHz = 800 kHz. Quantify rather than asserting; imperfect current sharing between phases limits the achievable cancellation, and that mismatch is itself a useful result.

Experiment 5: Efficiency map and phase shedding

Question: what is peak efficiency, with what uncertainty, and what is the optimal number of active phases at partial load?

Hero instrument: LMG671. At 25 W per phase the differences between shedding schedules are fractions of a percent, so accuracy is the whole justification.

Hero shots: an efficiency contour map over the operating envelope with an explicit uncertainty budget; and a family of 8 efficiency curves whose crossing points define the shedding schedule.

Procedure: efficiency map

1. Define the reference planes precisely and document them. State whether connector and cable losses are attributed to the converter. This decision must be stated in any published figure.
2. Sweep input voltage 20 to 55 V and per-phase current 0 to 8 A on a grid. Soak to thermal equilibrium at each point.
3. Record LMG671 input power, output power, efficiency, and both NTC temperatures.
4. Produce a contour map. Compare against the existing plots in Measurements/ (50 V, 64 V, 72 V) as a sanity check on the older hardware.

Procedure: phase shedding

1. Sweep total system power from ~100 W to full rated.
2. At each power level, measure efficiency with N = 1, 2, 4, 6, 8 phases active.
3. Plot the family of curves and locate the crossing points.
4. Derive the optimal shedding schedule and implement it in firmware.
5. Re-measure to confirm the predicted partial-load gain.

Uncertainty budget

At 99% efficiency the uncertainty budget is the result. Document:

• Instrument accuracy specification at the actual operating point, not the headline figure.
• Sense-lead placement and what is included inside the measurement boundary.
• Thermal drift over a 30-minute soak, measured by repeating one point.
• Repeatability across at least 3 independent runs of the same point.

A separate write-up on how not to overstate efficiency, derived from this section, would be strong content in its own right and costs nothing extra to produce.

Optional experiments

Experiment	Procedure summary	Hero instrument
Rare-event hunt	Zone trigger on SW-node overshoot above ~75 V. Run for hours across all 8 phases. Build a histogram of peak SW voltage over ~1011 switching cycles and extract the worst outliers.	MXO34, since ~4.5 M acquisitions/s is the only practical way to catch one-in-109 events
True switching energy	De-skew carefully, then integrate v*i per transition. The low-side device is ground-referenced (SW to PGND); the high-side device needs VIN - SW on the RT-ZISO. Plot Eon and Eoff against current and compare to the EPC23102 datasheet, noting that the datasheet figures are die-level and this measurement includes package and layout parasitics.	RT-ZISO plus MXO34
Bootstrap rail integrity	RT-ZISO on BOOT - SW while sweeping duty cycle up to the D = 0.7 ceiling imposed by HW_IOUT_MAXDUTY. Plot per-cycle CBOOT droop and the margin remaining to the high-side UVLO. Since no gate is observable, this is the only direct evidence that high-side drive stays healthy at high step-up ratio.	RT-ZISO
Inductor characterisation in situ	RT-ZISO across the inductor, integrate VL to get ripple current and solve for L across the 0 to 8 A range. Compare against the HW_L = 38 uH constant the current-limit law depends on.	RT-ZISO plus MXO34
MPPT tracking efficiency	Play a real cloudy-day irradiance profile into a solar array simulator. Compute energy captured divided by theoretical MPP energy, a different metric from conversion efficiency and rarely published honestly.	LMG671 data logger

The tracking-efficiency experiment requires a solar array simulator, which is not currently on the bench. The firmware contains an Ipvmodel in testing.c for simulation, but real tracking numbers need real hardware. See #Open items.

Data logging conventions

Store raw instrument exports alongside derived plots so results remain reproducible.

Measurements/
  YYYY-MM-DD_experiment/
    raw/          LMG671 and MXO34 exports, unmodified
    telemetry/    calibrate_mppt.py and CAN logs
    notes.md      operating point, firmware commit, instrument setup, de-skew values
    plots/        derived figures

Every session record must include: firmware git commit, hardware serial, ambient temperature, source and load configuration, instrument model and options, de-skew values, and soak duration. A figure without its operating point is not a result.

Publication checklist

Before posting any measurement:

1. Operating point stated on the figure, no exceptions.
2. Uncertainty stated for any efficiency or accuracy claim.
3. Measurement boundary defined for any efficiency claim.
4. Firmware commit recorded, so the result is reproducible.
5. Instrument model and relevant options named.
6. Result independently repeated at least once.

Suggested narrative order

Posting the unflattering result first is what makes the good result believable later.

1. Our MPPT runs at 55 C doing nothing. Experiment 1, opens with the problem.
2. Our own current sensor was lying. Experiment 2, resolves a mystery from post 1.
3. 8 ns of dead time cost us N degrees, measured on a part with no accessible gate pins. Experiment 3, the payoff.
4. What 8 interleaved GaN phases look like. Experiment 4, pure spectacle.
5. 99.x%, and here is our uncertainty budget. Experiment 5, the credibility close.

Open items

• Confirm RT-ZISO model bandwidth and isolation rating. Measure the actual SW edge rate first, which is likely of order 1 ns, then decide whether the probe is adequate for edge-timing work or only for the slower floating measurements.
• Confirm from the schematic whether the EPC23102 bootstrap capacitor is external and probeable. Item 1 of the floating-node list, and the bootstrap-integrity experiment, both depend on it.
• Confirm Kelvin access to both INA253 shunt terminals (Isense+ / Isense-). Without it the Experiment 2 cross-check cannot be made and the clipping question stays one-sided.
• Confirm LMG671 includes transient-recording and data-logger options.
• Source a solar array simulator, or arrange an alternative for tracking-efficiency work.
• Confirm which hardware revision is on the bench, and therefore which grounding rules apply.
• Coordinate with R&S applications engineering, who will co-develop the setups and usually have specific product messaging to hit.

See also

• Open-SEC Firmware/src/hardware/eoia656a.h, hardware parameter definitions
• calibrate_mppt.py, calibration and live telemetry tool
• MPPT_ID32+0-4.dbc, CAN database
• Measurements/, prior efficiency and loss plots